1. Field of the Invention
This invention relates to the circuits of reception portions for radio frequency (RF) communications employing AM modulation, such as the RF reception portion of a radio timepiece.
2. Description of Related Art
FIG. 1-FIG. 3 are circuit diagrams each showing a practicable example of a prior-art variable gain amplifier for auto gain control (AGC). Besides, FIG. 6 is a circuit diagram showing the basic constructional example of the RF reception portion of a prior-art radio timepiece.
In the variable gain amplifier shown in FIG. 1, a differential amplifier 1 is so configured that transistors T1 and T2 constitute a first differential pair, the absorption current of which is caused to flow to the drain of a transistor T5. Also, a differential amplifier 2 is so configured that a transistor T3 having a source resistance Rs1 connected to its source, and a transistor T4 having a source resistance Rs2 connected to its source constitute a second differential pair, the absorption current of which is caused to flow to the drain of a transistor T6. In order to connect the inputs and outputs of the differential amplifiers 1 and 2 in parallel, the positive inputs thereof (the gates of the transistors T1 and T3) and the negative inputs thereof (the gates of the transistors T2 and T4) are respectively connected to each other (whereby the differential amplifiers 1 and 2 receive the same differential inputs). Further, the positive-phase current outputs of the differential amplifiers 1 and 2 (the drains of the transistors T1 and T3) and the negative-phase current outputs thereof (the drains of the transistors T2 and T4) are respectively connected to each other (whereby the differential output currents of the differential amplifiers 1 and 2 are added up). The sum of the positive-phase output currents of the differential amplifiers 1 and 2 is caused to flow through a load resistance RL1 one end of which is connected to a supply voltage VDD, thereby to be converted into a negative-phase output voltage Vo−, while the sum of the negative-phase output currents thereof is caused to flow through a load resistance RL2 one end of which is connected to the supply voltage VDD, thereby to be converted into a positive-phase output voltage Vo+.
The absorption current transistor T5 of the differential amplifier 1 and that T6 of the differential amplifier 2 have their sources connected to each other, and further to a constant current circuit Is being an absorption current circuit, whereby a third differential amplifier is configured.
In the above construction, Is×M (where M denotes a value “0” to “1”) which is part of the constant current Is of the constant current circuit Is flows through the transistor T5, while Is (1−M) which is the remaining part of the constant current Is flows through the transistor T6. The allocation ratio M can be changed at will by a gain-control differential voltage Vgc which is applied across the inputs of the third differential amplifier (across the gates of the transistors T5 and T6).
Besides, in the above construction, the transfer conductance Gm1 of the differential amplifier 1 is determined by the absorption current flowing through the first differential pair. The transfer conductance Gm2 of the differential amplifier 2 is determined by the absorption current flowing through the second differential pair, and the source resistances Rs1 and Rs2. A gain which is attained from a differential input (the difference between the input voltages Vi+ and Vi−) to a differential output (the difference between the output voltages Vo+ and Vo−), is determined by a composite conductance Gm (=Gm1+Gm2) and the load resistances RL1 and RL2.
Letting I1 and I2 denote the currents which flow through the transistors T5 and T6, respectively, Gm(I1) denote the transfer conductance of the transistors T1 and T2 as is determined by the current I1, and Gm(I2) denote the transfer conductance of the transistors T3 and T4 as is determined by the current I2, the following relations hold:Is=I1+I2(I1=Is×M, I2=Is(1−M), 0<M<1)Gm1=Gm(I1)/2Gm2=1/(Rs1+Rs2+(2/Gm(I2)))Accordingly, the transfer conductances Gm1 and Gm2 are appropriately changed by controlling the current allocation ratio M stated above, whereby the maximum gain can be attained when the constant current Is has flowed through the differential amplifier 1 (at M≅1), and the minimum gain when the constant current Is has flowed through the differential amplifier 2 (at M≅0). That is, the allocation ratio M between the currents to flow through the differential amplifiers 1 and 2 is controlled by the gain-control differential voltage Vgc, whereby the variable gain amplifier capable of attaining any desired gain between the maximum gain and the minimum gain can be realized.
The variable gain amplifier circuit in FIG. 2 performs an operation equivalent to that of the circuit in FIG. 1 in such a way that transistors T1-T4 and load resistances RL1-RL2 are made the same transistors T1-T4 and load resistances RL1 -RL2 as in the circuit shown in FIG. 1, respectively, that a resistance Rs in FIG. 2 is set at the value (Rs=Rs1+Rs2) of the sum of the resistances Rs1 and Rs2 in FIG. 1, and that the sum of the sizes of transistors T6a and T6b in FIG. 2 is equalized to the size of the transistor T6 in FIG. 1 (T6a size =T6b size, T6 size=T6a size+T6b size).
In the variable gain amplifier circuit shown in FIG. 3, a first differential pair is constituted by transistors T1 and T2 to which differential input voltages Vi+ and Vi− are respectively inputted, and a second differential pair is constituted by transistors T3 and T4 to which the differential input voltages Vi+ and Vi− are not inputted. The allocation between an absorption current to flow through the first differential pair and an absorption current to flow through the second differential pair is changed by changing the potential differential between a DC bias VB (FIG. 4 exemplifies an equivalent circuit therefor, in which either a resistance R or a choke coil L is sometimes omitted) connected to a differential input and a gain control voltage Vgc, so as to change the transfer conductance Gm1 of the first differential pair which is pertinent to amplification. Thus, a gain which is attained from the differential input (the difference between the voltages Vi+ and Vi−) to a differential output (the difference between voltages Vo+ and Vo−) is changed. Incidentally, the second differential pair constituted by the transistors T3 and T4 functions to hold the DC bias of the output voltages Vo+ and Vo− constant without changing them.
The DC bias VB is sometimes included in the differential input voltages Vi+ and Vi−.
Although FIGS. 1-3 show the examples each of which is constructed of the transistors of MOS type, such a variable gain amplifier can also be constructed of field effect transistors of junction type or transistors of bipolar type.
In Japan, Communications Research Laboratory is incessantly transmitting standard radio waves serving as frequency standards, at 40 kHz from a transmitting station located in Fukushima Prefecture and at 60 kHz from a transmitting station located in Saga Prefecture.
Time information (Japan Standard Time) based on an AM-modulated signal is superposed on each of the standard radio waves. The standard radio wave is received, and a time code is restored and interpreted, whereby a time can be known at an accuracy which corresponds to the degree of a delay time (several mess) involved from the transmission of the radio wave till the arrival thereof.
When the function of correcting a time by employing the time information is bestowed on a timepiece, the timepiece in which the above time accuracy is always kept can be realized as a so-called “radio timepiece”.
The image of the standard radio waves is shown in FIG. 5. Each of the standard radio waves in Japan is the AM-modulated signal which has the above transmission frequency as a carrier, and which consists only of two amplitude states of a large amplitude of 1 and a small amplitude of 0.1 (modulation percentage: 90%). The standard radio wave has a transmission speed of 1 (one) bit/sec. When one bit length consists of the large amplitude state for 200 msec and the small amplitude state for the remaining 800 msec, a code “M” (mark signal) is expressed; when it consists of the large amplitude state for 800 msec and the small amplitude state for the remaining 200 msec, a code “0” is expressed; and when it consists of the large amplitude state for 500 msec and the small amplitude state for the remaining 500 msec, a code “1” is expressed. The time code is formed by combining the three statuses.
The time code is a code train having a length of 60 bits as a unit, which begins with the “M” code, in which the information items of minutes, o'clock, days summed up since New Year's Day, the dominical year, and a day of the week are delimited by the “M” codes, and which ends in the “M” code. Accordingly, the delimitation and head positions of time codes can be respectively identified by detecting the positions of “M” code successions. (the tail of the preceding code train and the head of the next code train).
In the circuit of the RF reception portion of the radio timepiece as shown in FIG. 6, a bar antenna L and a tuning capacitor C are tuned to the standard radio wave so as to selectively receive this standard wave and to input it to a preamplifier PA. A bias circuit VB (the equivalent circuit example of which is shown in FIG. 4) feeds an input bias to the preamplifier PA.
A variable gain amplifier GCA receives the output of the preamplifier PA as its input Vi, and amplifies the input Vi at a gain complying with a control from a gain control terminal.
A band-pass filter BPF removes a low-frequency component and a high-frequency component which are noise components outside the necessary bandwidth of the output of the variable gain amplifier GCA.
A peak detection circuit PDet which is constituted by a first rectification circuit Rec1, a first peak holding capacitor C1 and a first discharge resistance R1, detects the peak value of the output Vo of the band-pass filter BPF so as to output a peak value voltage Vp.
A gain control amplifier DA feeds the gain control terminal of the variable gain amplifier GCA with a DC voltage for lowering the gain of the variable gain amplifier GCA, in a case where the output Vp of the peak detection circuit PDet is larger than a first reference voltage VR1, and with a DC voltage for heightening the gain, in a case where the former is smaller than the latter. Thus, a control (negative feedback control) is performed so that the potential difference between the output Vp of the peak detection circuit PDet and the first reference voltage VR1 may become substantially zero. As a result, the large amplitude side of the output amplitude Vo of the band-pass filter BPF becomes a substantially constant level.
A low-pass filter LPF which is insertively connected to the output of the gain control amplifier DA, is endowed with a time constant so as to prevent the gain control of the variable gain amplifier GCA from becoming unstable.
An envelope detection circuit SDet which is constituted by a second rectification circuit Rec2, a second peak holding capacitor C2 and a second discharge resistance R2, outputs a voltage which becomes the peak value envelope of the RF amplitude value of the output Vo of the band-pass filter BPF (as indicated by a broken-line waveform in FIG. 7).
A comparator Comp compares the output of the envelope detection circuit SDet with a second reference voltage VR2 (set at the intermediate value between the high and low voltages of the envelope detection output). It outputs a logic signal “H” in a case where the output of the envelope detection circuit SDet is larger than the second reference voltage VR2, and a logic signal “L” in a case where the former is smaller than the latter.
The time length of the logic signal “H” or “L” is identified by a microcomputer or the like not shown, thereby to identify which of the codes “M”, “0” and “1” of the time code train. The microcomputer recognizes the current time by decoding the received time code, and it corrects and displays the time (as radio timepiece functions).
Since the timepiece may be set aright several times a day, a power source circuit Reg which controls power supply from an external power source VDD to the individual circuits in accordance with a control signal PON (for power ON/OFF, constant voltage supply, etc.) is disposed so as to avoid wasteful power dissipation.
In the example of FIG. 6, the band-pass filter BPF is sometimes omitted in a case where the output noise of the variable gain amplifier GCA is small. Besides, an appropriate buffer circuit which satisfies the terminating condition of the band-pass filter BPF and which can drive the first rectification circuit Rec1 as well as the second rectification circuit Rec2 is located between the band-pass filter BPF and the first rectification circuit Rec1 as well as the second rectification circuit Rec2. Further, the low-pass filter LPF is sometimes omitted in a case where the gain control amplifier DA includes an appropriate low-pass filter characteristic.
The radio timepiece requires AGC (auto gain control) which can cope with inputs in a wide range of approximately 1 μVrms -100 mVrms. In some cases, therefore, the reception preamplifier PA is also constructed as part of the variable gain amplifier GCA (as a control indicated by a broken line drawn to the reception preamplifier PA in FIG. 6).
In the ensuing description, a circuit which corresponds to a portion including the variable gain amplifier GCA, gain control amplifier DA and low-pass filter LPF in FIG. 6 will be sometimes expressed as a variable gain amplifier block GCAb, and a circuit which corresponds to a portion with the band-pass filter BPF added to the block GCAb will be sometimes expressed as a gain control amplifier block GCA-B. Further, a circuit which corresponds to a portion including the gain control amplifier block GCA-B and peak detection circuit PDet will be sometimes expressed as an auto gain control circuit AGC or an AGC circuit.
Since each standard radio wave to be received by the radio timepiece is of AM modulation scheme, a linearity is required of the amplification of the auto gain control circuit AGC. Besides, since the number of the transmitting stations of the standard radio waves is small, places which range from positions underneath transmission antennae to positions at very long distances need to be capable of receiving the standard radio waves, and a wide AGC range is necessitated. It is accordingly desired to realize a variable gain amplifier in which the linearity is always ensured and the variable gain range of which is wide.
In each of the variable gain amplifiers shown in FIG. 1 and FIG. 2, the minimum gain which is determined by the transfer. conductances Gm(Is) of the transistors T1-T4 and the resistances Rs1 and Rs2 (or the combined resistance Rs) is existent, and a variable gain range becomes narrow unless the transfer conductances Gm(Is) of the transistors T1-T4 cannot be made sufficiently large as compared with the inverse number of the source resistance Rs. Besides, since the differential pairs based on the transistors T1-T4 and the differential pair of the transistors T5-T6 are serially connected between power source voltages, the minimum operating supply voltage cannot be made small, and hence, the variable gain amplifier is unsuited to a low supply voltage operation such as of battery drive (having a supply voltage of 1.5 V). It is accordingly desired to realize a variable gain amplifier which has a wide variable gain range and which can lower the minimum operating voltage.
The variable gain amplifier circuit in FIG. 3 includes only one differential pair between power source voltages, and is therefore suited to a low supply voltage operation. However, in a case where the input potential has increased and where the gain control voltage Vgc is heightened so as to lower the gain by an AGC operation, an output dynamic range and a linear input range narrow as the current through the differential pair (transistors T1 and T2) pertinent to the gain decreases (though the gain is lowered by the current decrease). Therefore, as the amplifier circuit enters a large input potential (low gain operation) region, the AGC operation shifts to a limit amplification operation, and the linearity worsens.
It is accordingly desired to realize a variable gain amplifier whose output dynamic range is kept even in the large input potential (low gain operation) region, and whose linear input range is expanded with increase in the input potential, so that the linearity can be always kept.
In case of the radio timepiece of wall clock type or the like, the direction of the timepiece changes depending upon the place of installation, and also the sense of the bar antenna of the reception portion changes. An antenna reception gain changes depending upon the sense of the bar antenna. With the single antenna as in the reception portion of the radio timepiece in FIG. 6, therefore, a situation can occur where a reception level is zero in a certain sense. It is accordingly desired to realize a bar antenna mounting method/reception method in which, even when the direction of the radio timepiece has changed, a predetermined reception level or above can be ensured.
In the case where the reception preamplifier PA is the differential input amplifier, the connection of the bias circuit(s) VB to both or either of differential input differentially amplifies a noise component generated by the bias circuit VB and degrades the S/N ratio (signal-to-noise ratio) of the reception portion. It is accordingly desired to realize a reception preamplifier in which the influence of noise generated by the bias circuit VB is suppressed to improve the S/N ratio of the reception portion and to afford a favorable minimum reception sensitivity characteristic.
Each standard radio wave conforms to the AM modulation scheme, and the information transmission thereof is as very slow as 1 bit/sec, so that an AGC scheme in which the ratio between the large and small amplitude levels is held correct for a long time is required. Therefore, it becomes necessary to enlarge the holding time constant of the peak detection circuit PDet or the time constant of the low-pass filter LPF. When the time constant is enlarged, a large time constant capacitance is necessitated, a time period since the start of reception till the stabilization of AGC becomes long, and an AGC follow-up speed in the case of a reception level fluctuation lowers.
It is accordingly desired to realize an AGC circuit which can attain such an AGC operation that the increase of the time constant capacitance can be suppressed to hold the ratio between the large and small amplitude levels correct for long, that the time period since the start of reception till the stabilization of the AGC is short, and that the follow-up speed in the case of the reception level fluctuation is high.
In peak-value envelope detection for the AM-modulated wave as employs a rectifier, a detection waveform rises fast and falls slowly as indicated by a broken-line waveform in FIG. 7, so that a pulse width precision for discriminating the time code degrades to lower a reception time accuracy. It is accordingly desired to realize a detection circuit which can produce an output precisely corresponding to a peak-value envelope.